JPH04532B2 - - Google Patents

Info

Publication number
JPH04532B2
JPH04532B2 JP61095747A JP9574786A JPH04532B2 JP H04532 B2 JPH04532 B2 JP H04532B2 JP 61095747 A JP61095747 A JP 61095747A JP 9574786 A JP9574786 A JP 9574786A JP H04532 B2 JPH04532 B2 JP H04532B2
Authority
JP
Japan
Prior art keywords
light
primary mold
receiving
side primary
emitting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61095747A
Other languages
English (en)
Japanese (ja)
Other versions
JPS62251616A (ja
Inventor
Hajime Kashida
Shigenori Kitanishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP61095747A priority Critical patent/JPS62251616A/ja
Publication of JPS62251616A publication Critical patent/JPS62251616A/ja
Publication of JPH04532B2 publication Critical patent/JPH04532B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding

Landscapes

  • Optical Transform (AREA)
  • Light Receiving Elements (AREA)
JP61095747A 1986-04-24 1986-04-24 ホトインタラプタ Granted JPS62251616A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61095747A JPS62251616A (ja) 1986-04-24 1986-04-24 ホトインタラプタ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61095747A JPS62251616A (ja) 1986-04-24 1986-04-24 ホトインタラプタ

Publications (2)

Publication Number Publication Date
JPS62251616A JPS62251616A (ja) 1987-11-02
JPH04532B2 true JPH04532B2 (en]) 1992-01-07

Family

ID=14146085

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61095747A Granted JPS62251616A (ja) 1986-04-24 1986-04-24 ホトインタラプタ

Country Status (1)

Country Link
JP (1) JPS62251616A (en])

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100542869B1 (ko) * 1996-10-22 2006-05-23 로무 가부시키가이샤 포토인터럽터
JP5011799B2 (ja) * 2006-04-10 2012-08-29 三菱電機株式会社 光学式エンコーダ
JP6429621B2 (ja) * 2014-02-18 2018-11-28 エイブリック株式会社 光センサ装置および光センサ装置の製造方法

Also Published As

Publication number Publication date
JPS62251616A (ja) 1987-11-02

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees